16-bit multiplying DAC — signal conditioning for gain and offset.
Overview
The AD5545 is a 16-bit dual-channel multiplying DAC used to condition the TIA output before it reaches the ADC. It serves two roles:
| Channel | Role | Default | Effect |
|---|
| ChA | Gain control | 100% | Scales TIA feedback resistance → sensor sensitivity |
| ChB | Offset cancel | Set at ZERO cal | Subtracts sensor baseline in clean air |
Byte 0: [ 0 0 0 0 0 A1 A0 ] — Channel address (ChA=01, ChB=10)
Byte 1: [ D15 D14 D13 D12 D11 D10 D9 D8 ]
Byte 2: [ D7 D6 D5 D4 D3 D2 D1 D0 ]
3 bytes per write, MSB first. CS is held low for the entire transaction. After writing one or both channels, LDAC is pulsed low for ≥1 µs to latch the new value.
Control Pins
| Pin | Function | Idle State | Description |
|---|
| CS | Active-low chip select | High | Must be held low during SPI frame |
| LDAC | Latch | High | Pulse low (≥1 µs) to update DAC register |
| MSB | Reset mode | High | High = mid-scale (32768), Low = zero-scale (0) |
| RS | Reset | High | Pulse low (≥10 µs) to reset both channels |
Percent-to-Code Conversion
// bsp/src/hardware/ad5545.rs
pub fn percent_to_code(percent: f32) -> u16 {
let pct = percent.clamp(0.0, 100.0);
(pct * 65535.0 / 100.0 + 0.5) as u16
}
| % | Code | Voltage (relative) |
|---|
| 0% | 0 | 0 V |
| 50% | 32768 | ½ × VREF |
| 100% | 65535 | VREF |
DAC Behaviour During Calibration
| Event | ChA | ChB | LDAC pulse |
|---|
| Power-on | 100% | 0% | Yes |
ZERO cmd | Unchanged | Computed offset % | Yes (via bias_task) |
SPAN cmd | Gain % | Unchanged | Yes |
Troubleshooting Notes
A previous issue arose from using ExclusiveDevice (wrong SPI timing) instead of ArbiterDevice. The AD5545 requires adequate CS settling — ArbiterDevice with an explicit embassy_time::Delay provides this. See docs/hardware/dac-troubleshooting.md in the firmware repo.